Patent number 8553468 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Nonvolatile flash memory devices store information in the form of charge in a flash cell. A flash cell typically includes a complementary metal oxide semiconductor (CMOS) transistor with an additional floating metal gate between the substrate and the transistor's gate. In operation, a charge is stored in the floating gate. The charge is injected to the floating gate during an operation known as programming The charge may be removed during an operation known as an erase operation. As the charge stored in the floating gate may vary, it is possible to store information representing more than just one bit per flash cell by using several charge levels to represent different sequences (or values) of a number of bits. Otherwise described, to represent different values related to different bit sequences, different charges (which may be observed as different voltage levels) may be stored in a floating metal gate of a flash cell.
"Typically, P/E cycles are applied to a block of flash cells. A block erase operation typically involves charging all cells in the block to some high programming level, and applying a set of erase pulses. For example, as shown in FIG. 1, the pulse duration and pulse magnitude may be controlled during the erase process. This may be done, for example, by setting initial and incremental step values of time (e.g., Tstart and .DELTA.T), and pulse magnitude (Vstart and .DELTA.V), as well as total number of pulses applied. After each pulse (or set of pulses) an internal module or the controller verifies that all cells in the block are erased. If so, the erase process ends. Otherwise, additional erase pluses are applied. Additional pulses typically have increased erase voltage or increased pulse duration. This process may continue until the number of erase pluses exceeds the maximum allowable number of erase pluses. A single program/erase (P/E) cycle is defined to be a programming phase of a block of flash cells and the activation of an erase command, which in turn may cause a controller to perform and/or activate the erase-verify procedure described above.
"Erase operations are known to cause deterioration in the reliability of a flash cell's storage ability, due to the high voltages that must be applied during erase operations. While individual erase operations may not have noticeable effect, over many erase cycles, they may have a cumulative deleterious effect on the cells. Therefore, reducing these effects can dramatically improve the flash cell's reliability and increase the overall amount of P/E cycles per physical block.
"A drawback of current systems and methods is that, following a number of program/erase (P/E) cycles applied to a flash cell, electric charge may be accumulated or trapped in a flash cell. This effect is referred to as cycling effect. Another effect is known as retention, in which the cells discharge as time goes by. With retention, an effective working window of voltage levels may shrink, shift and/or otherwise change, resulting an increased error rate that may be related to reading data from the flash cell and/or removing data from the flash cell. Retention effects are known to become significantly worse as the number of P/E cycles increases."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Embodiments of the invention are directed to managing a memory component. A method may include performing a first erase operation according to a first set of erase parameters, determining a result of the first erase operation, modifying the first set erase parameters based on the result to produce a second set of erase parameters and performing a second erase operation according to a second set of erase parameters. A condition parameter may be maintained and/or updated based erased parameters used in an erase procedure and/or based on a result of an erase procedure. Erase parameters may be set based on a condition parameter. Specifically, erase parameters such as the number of pulses applied, pulse duration, voltage level and total amount of energy (or measurements which are proportional to the energy) used in an erase procedure may be recorded and/or used to update a condition parameter that may reflect a condition or age of a memory component. Erase parameters may be updated dynamically and/or adaptively. For example, based on a result of a first erase cycle, erase parameters may be updated or modified and a second erase cycle may be performed based on the modified erase parameters."
URL and more information on this patent, see: Sabbag, Erez;
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