The patent's assignee for patent number 8555218 is
News editors obtained the following quote from the background information supplied by the inventors: "Synthesis tools are used to define an IC design and/or to map the design to a technology that is used to manufacture the IC. Such tools typically receive a design in one particular format and then perform a series of transformations on this format to define the design in another particular format. For instance, some synthesis tools receive the IC design in a register transfer language (RTL) format, and through a series of transformations, produce a circuit representation of the design that has been mapped to the technology used to manufacture the IC.
"In performing the transformations, synthesis tools often must select between various available implementations for a given segment or function of the design. Typically, the synthesis tools make these decisions without sufficient data regarding constraints (e.g., timing data, area data, etc.) on the design. For example, a synthesizer might need to select a particular implementation of an adder. While different implementations of the adder may be functionally equivalent, the adders are not structurally equivalent. As such, each implementation is associated with different timing characteristics, area characteristics, etc. The synthesizer might need to select between the different adder implementations early in the synthesis flow. At the early stages, the synthesizer may not have sufficient constraint information (e.g., timing information about the expected signal delay or congestion information) to determine which of the viable options best satisfies the constraints. In such situations, synthesizers typically make greedy decisions that are not based on realistic data regarding design constraints.
"Some synthesis tools today work in conjunction with placement tools during a multi-stage electronic design automation (EDA) process to improve the overall placement of the design. For instance, when a placer determines that a particular set of circuit modules in the design violates a particular design constraint, the placer will direct a synthesizer to provide an alternative implementation for the particular set of circuit modules to satisfy the particular design constraint. In response to such a request, the synthesizer might provide a better solution for the particular set of circuit modules that satisfies the particular design constraint. However, the new solution of the synthesizer might adversely affect the placement of other circuit modules causing the other circuit modules to violate one or more design constraints. This results in a cascading effect where a change in any one location of the design affects other circuits elsewhere within the design. As such, the prior art processes are prone to iteratively repeating until a preferred solution is determined that not only satisfies constraints for a particular implementation for a set of circuits, but that also satisfies constraints for other circuit modules affected by the placement of the particular selected implementation for the set of circuit modules. Such iterative repeating requires an exponential number of computations to converge to a solution that satisfies all constraints.
Most Popular Stories
- Bipartisan Budget Deal Gets Key Support in House
- Bitcoin Clones Lurch Onto Financial Scene
- Clinton to Keynote Annual Simmons Leadership Conference
- TFA Recruiting DACA Recipients
- Scotch Whisky Sales Raise Distillers' Spirits
- Holiday Shopping Off to a Slow Start This Season
- Fake Deaf Interpreter Was Hallucinating, Has Schizophrenia
- Tea Party Glum in Face of Bipartisan Budget Deal
- Budget Deal Will Cut 220,000 Californians Out of Jobless Benefits
- Health Coverage Disparities Emerge Among States